A Synopsys Webinar Detailing IP Requirements for Advanced AI Chips
The rapid advancement of generative AI has led to a significant increase in compute power requirements for advanced designs. Over the past five to six years, the demand for compute power has surged by more than 10,000 times. This heightened demand is affecting the entire SoC design process. Engineers are now challenged to push beyond 1 trillion transistors per chip and develop systems capable of meeting these escalating computational needs.
Generative AI is dramatically changing the compute power that must be delivered by advanced designs. This demand has risen by more than 10,000 times in the past five to six years. This increased demand has impacted the entire SoC design flow. We are now faced with going beyond 1 trillion transistors per chip, and systems now consist of many chips in a highly sophisticated package. Synopsys recently presented a webinar on these trends and offered some excellent strategies to tame the on-going demands of GenAI.
About the Presenter
Dr. Manuel Mota, the senior product manager responsible for the die-to-die interface IP product line at Synopsys, has been with the company for over 15 years. He has held leadership roles at MIPS Technologies and Chipidea and began his career as a researcher at CERN, the European Organization for Nuclear Research. Dr. Mota has authored multiple technical papers on multi-die design.
About the Webinar
Manuel begins the webinar with an overview of the impact generative AI has had on technology evolution. He shares insights on trends such as larger compute chips, advanced packaging, memory architectures, and die-to-die bandwidth increases. Manuel then delves into SoC architectures focusing on higher compute performance and discusses key technologies for multi-die designs.
Die-to-Die Communication
Manuel discusses the benefits of 40/64G speeds in die-to-die communication, highlighting the standards and Synopsys IP solutions for 64Gbps die-to-die communication. He details the features and capabilities of the IP, along with real-world applications.
Custom HBMs
Custom HBMs offer a memory bandwidth advantage and flexibility. Manuel explains how this approach enables novel SoC memory architectures, outlining the benefits and strategies associated with it.
3D Stacking
Manuel explores the power savings and performance benefits of 3D stacking, sharing commercial examples and discussing architectural challenges and benefits. He covers multi-die interconnect approaches and assembly options, highlighting design challenges and the importance of choosing the right approach for each project.
The webinar concludes with an overview of the comprehensive set of solutions that Synopsys provides for heterogeneous integration. A summary of the discussion is provided, followed by an informative live Q&A session.
If you are considering a multi-die approach for advanced AI technology, watching this webinar is highly recommended. Dr. Manuel Mota's expertise and insights make it a valuable resource for design teams. You can access the replay of the webinar here.